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Victor Torres

Verification Engineer

Microchip Technology Inc.

About

Design Verification Engineer at Microchip Technology with expertise in UVM-based testbench development, SystemVerilog, and ARM Cortex SoC verification. Passionate about leveraging automation and emerging technologies to enhance verification efficiency. Master's degree in Computer Engineering from ASU with research background in FPGA design and deep learning implementations. Recipient of the Fulbright García-Robles Scholarship.

Experience

Design Verification Engineer

June 2022 - Present

Microchip Technology Inc. • Chandler, AZ

  • Formulated verification requirements by analyzing design specifications
  • Developed constrained-random sequences in UVM-based SystemVerilog testbenches and C-based test programs to verify ARM Cortex-based SoCs and IP blocks (Programmable Flash Controller, Ethernet Controller)
  • Collaborated with design and architecture teams to debug microcontroller subsystems and submodule designs
  • Developed and deployed Python scripts to automate regression testing and result analysis, reducing manual effort and accelerating verification efficiency
  • Led adoption of internal RAG-based AI chatbot enhancements as cross-site AI/ML workgroup representative; presented solution to design team

Research Assistant

August 2020 - May 2022

Arizona State University • Tempe, AZ

  • Implemented algorithm for efficient object tracking running accelerated deep learning model on Xilinx FPGA board
  • Trained neural network architectures to detect objects recorded by neuromorphic (event) camera
  • Summer research project with Astrobotic for Space Force Small Business grant
  • Published research on FPGA-accelerated visual tracking in IEEE Access journal

Product Coordinator

May 2018 - October 2019

Robert Bosch • Cd. Juárez, México

  • Managed implementation of engineering changes on Electronic Control Units (ECUs) and ultrasonic park-assist sensors without affecting production line downtime
  • Implemented product re-validation project to reduce aftermarket backlog by 90%, coordinating a cross-functional team

Education

Master of Science in Computer Engineering

May 2022

Arizona State University • Tempe, AZ

GPA: 3.9 | Focus: Digital Design, Hardware Verification, VLSI

Bachelor of Science in Mechatronics Engineering

May 2018

Instituto Tecnológico y de Estudios Superiores de Monterrey • Cd. Juárez, México

GPA: 4.0 (94/100)

Skills

Programming Languages

SystemVerilog Python C

Development Tools & Technologies

Linux Git JIRA Confluence Bash FPGA Design

Verification & Design

UVM Testbench Development Verification Planning SoC Verification Deep Learning on FPGA Test Automation

Publications & Awards

Adaptive Subsampling for ROI-Based Visual Tracking: Algorithms and FPGA Implementation

IEEE Access • August 2022

Fulbright García-Robles Scholarship

Awarded a fully-funded, binational sponsored grant to study master's degree in the USA

Contact

Email: v.torres621@gmail.com

Location: Chandler, AZ