Victor Torres

I am a Master's in Computer Engineering student at ASU. Currently working at the Imaging Lyceum, where I perform research on computer vision, machine learning and Field Programmable Gate Arrays (FPGAs).

Email / CV / Github

	Arizona State University Master's in Computer Engineering August '20 - May '22
	Instituto Tecnológico y de Estudios Superiores de Monterrey Bachelor's in Mechatronics Engineering August '14 - May '18

Research Assistant | Imaging Lyceum at ASU
Aug '20 - May '22

Deploying computer vision and machine learning algorithms on FPGAs.
Improving imaging for outdoor robotic vision applications with neuromorphic (event) cameras.

Electrical Engineer | Torres Electric
Oct '19 - Aug '20

Short-circuit, arc flash and protection coordination studies.
Power quality measurement equipment installation.
Thermography Studies on electrical equipment.

Product Coordinator | Robert Bosch GmBH
Aug '17 - Oct '19

Responsible for all activities related to Manufacturing Engineering of Electronic Control Units (ECUs).
Engineering change management implementation for existing products.
Coordination of trial runs to meet project deliverables (i.e. Initial samples, EWAK-series, PV-runs).

	FPGA implementation of adaptive subsampling. Implementation of an efficient adaptive subsampling pipeline involving a neural-network-based object detector (YoloV3, tinyYoloV3, ECO) and classical computer vision algorithms on a Xilinx FPGA board.
	Event camera object tracker Trained off-the-shelf neural networks to detect objects from a neuromorphic (event) camera dataset. Leveraged use of representation techniques found in literature such as voxel-grid and intensity reconstruction from events.

	N-MNIST object tracker. Trained custom Convolutional Neural Network to perform detection and classification of MNIST digits captured with an event camera.
	Denoising neural network. Trained UNet to correct noisy images. Custom dataset generated by simulating photon-shot noise, read noise and ADC noise.
	Conv-Pool engine design. Developed a 4x4 convolution and maxpooling engine for deep learning applications and implemented on 7nm CMOS technology. Wrote behavioral System Verilog module. Synthesized using Design Compiler. Performed palce-and-route using Innovus. Accomplished DRC and LVS clean in Virtuoso. Assured functional verification at every step.